Datasheet

Data Sheet AD5253/AD5254
Rev. C | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5253/
AD5254
TOP VIEW
(Not to Scale)
W0
1
B0
2
A0
3
AD0
4
5
W1
6
B1
7
A1
8
SDA
9
V
SS
10
V
DD
W3
B3
A3
AD1
20
19
18
17
16
DGND
SCL
W2
B2
A2
15
14
13
12
11
03824-0-002
WP
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 W0 Wiper Terminal of RDAC0. V
SS
≤ V
W0
≤ V
DD
.
2 B0 B Terminal of RDAC0. V
SS
≤ V
B0
≤ V
DD
.
3 A0 A Terminal of RDAC0. V
SS
≤ V
A0
≤ V
DD
.
4
AD0
I
2
C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
5
WP
Write Protect, Active Low. V
WP
≤ V
DD
+ 0.3 V.
6 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W1
≤ V
DD
.
7 B1 B Terminal of RDAC1. V
SS
≤ V
B1
≤ V
DD
.
8 A1 A Terminal of RDAC1. V
SS
≤ V
A1
≤ V
DD
.
9 SDA Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain
MOSFET requires pull-up resistor.
10 V
SS
Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V
DD
– V
SS
≤ +5.5 V. If V
SS
is used
rather than grounded in dual supply, V
SS
must be able to sink 35 mA for 26 ms when storing data to EEMEM.
11 A2 A Terminal of RDAC2. V
SS
≤ V
A2
≤ V
DD
.
12 B2 B Terminal of RDAC2. V
SS
≤ V
B2
≤ V
DD
.
13 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W2
≤ V
DD
.
14 SCL Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. V
SCL
≤ (V
DD
+ 0.3 V). Pull-up
resistor is recommended for SCL to ensure minimum power.
15 DGND Digital Ground. Connect to system analog ground at a single point.
16 AD1 I
2
C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
17 A3 A Terminal of RDAC3. V
SS
≤ V
A3
≤ V
DD
.
18 B3 B Terminal of RDAC3. V
SS
≤ V
B3
≤ V
DD
.
19 W3 Wiper Terminal of RDAC3. V
SS
≤ V
W3
≤ V
DD
.
20 V
DD
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V
DD
– V
SS
≤ +5.5 V.
V
DD
must be able to source 35 mA for 26 ms when storing data to EEMEM.