Datasheet

Data Sheet AD5253/AD5254
Rev. C | Page 7 of 32
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V
DD
= 3 V and 5 V.
Table 3.
Parameter
1
Symbol Conditions Min Typ
2
Max Unit
INTERFACE TIMING
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus-Free Time Between Stop and Start t
1
1.3 μs
t
HD;STA
Hold Time (Repeated Start) t
2
After this period, the first clock pulse is
generated.
0.6 μs
t
LOW
Low Period of SCL Clock t
3
1.3 μs
t
HIGH
High Period of SCL Clock t
4
0.6 μs
t
SU;STA
Set-up Time for Start Condition t
5
0.6 μs
t
HD;DAT
Data Hold Time t
6
0 0.9 μs
t
SU;DAT
Data Set-up Time t
7
100 ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Set-up Time for Stop Condition t
10
0.6 μs
EEMEM Data Storing Time t
EEMEM_STORE
26 ms
EEMEM Data Restoring Time at Power-On
3
t
EEMEM_RESTORE1
V
DD
rise time dependent. Measure without
decoupling capacitors at V
DD
and V
SS
.
300 μs
EEMEM Data Restoring Time upon Restore
Command or Reset Operation
3
t
EEMEM_RESTORE2
V
DD
= 5 V. 300 μs
EEMEM Data Rewritable Time
4
t
EEMEM_REWRITE
540 μs
FLASH/EE MEMORY RELIABILITY
Endurance
5
100 K cycles
Data Retention
6, 7
100 Years
1
See Figure 23 for location of measured values.
2
Typical values represent average readings at 25°C and V
DD
= 5 V.
3
During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.
4
Delay time after power-on or reset before new EEMEM data to be written.
5
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000 cycles.
6
Retention lifetime equivalent at junction temperature T
J
= 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
7
When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I
2
C interface at these pins conducts a current of
about 0.8 mA at V
DD
= 5.5 V and 0.2 mA at V
DD
= 2.7 V.