Datasheet
Data Sheet AD5253/AD5254
Rev. C | Page 23 of 32
03824-0-038
+5V
R1
AD1
AD0
N142
4
+5V
R2
X
AD1
AD0
N2
X
+5
P2
Y
P2
Y
P3
X
R3
X
R3
Y
N3
Y
AD1
AD0
AD1
AD0
4
4
4
+5V
P4
R4
+5V
2 4
DECODER
4
2 4
DECODER
4
2 4
DECODER
4
2 4
DECODER
Figure 38. Four Devices with AD1 and AD0 of 00
TERMINAL VOLTAGE OPERATION RANGE
The AD5253/AD5254 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Ter m i nal A , Termin al B, or Ter m inal W that exce e d V
DD
are
clamped by the forward-biased diode. Similarly, negative signals
on Termi n al A, Te r m inal B, or Ter m i nal W t h at are more
negative than V
SS
are also clamped (see Figure 39). In practice,
users should not operate V
AB
, V
WA
, and V
WB
to be higher than
the voltage across V
DD
to V
SS
, but V
AB
, V
WA
, and V
WB
have no
polarity constraint.
03824-0-039
V
DD
A
W
B
V
SS
Figure 39. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at Ter minal A , Termin a l B, and Termin a l W (Figu re 3 9 ), it is
important to power V
DD
/V
SS
before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that V
DD
/V
SS
are powered unintentionally and may affect the
user’s circuit. Similarly, V
DD
/V
SS
should be powered down last.
The ideal power-up sequence is in the following order: GND,
V
DD
, V
SS
, digital inputs, and V
A
/V
B
/V
W
. The order of powering
V
A
, V
B
, V
W
, and the digital inputs is not important, as long as
they are powered after V
DD
/V
SS
.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 μF to 10 μF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 40 illustrates the basic
supply-bypassing configuration for the AD5253/AD5254.
03824-0-040
V
DD
V
DD
V
SS
V
SS
GND
C3
AD5253/AD5254
C4
C1
C2
10F
10F
0.1F
0.1F
Figure 40. Power Supply-Bypassing Configuration
The ground pin of the AD5253/AD5254 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5253/AD5254 ground terminal should be joined
remotely to the common ground (see Figure 40).