Datasheet

Data Sheet AD5253/AD5254
Rev. C | Page 17 of 32
From Master to Slave
From Slave to Master
S = start condition
P = stop condition
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
AD1, AD0 = I
2
C device address bits, must match with the logic states at Pins AD1, AD0
R/
W
= read enable bit at logic high; write enable bit at logic low
CMD/
REG
= command enable bit at logic high; register access bit at logic low
C3, C2, C1, C0 = command bits
A2, A1, A0 = RDAC/EEMEM register addresses
1 READ
03824-0-009
S 0 1 0 1 1 A
D
1
A
D
0
1 A PA
RDAC_N OR EEMEM_N
REGISTER DATA
RDAC_N + 1 OR EEMEM_N + 1
REGISTER DATA
SLAVE ADDRESS (N BYTES + ACKNOWLEDGE)
A
Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)
P
S SLAVE ADDRESS
0 WRITE
SLAVE ADDRESS
INSTRUCTIONAL AND
ADDRESS
A
1
S
03824-0-010
REPEATED START
1 READ
A0
A
(N BYTES + ACKNOWLEDGE)
RDAC OR
EEMEM DATA
A/A
Figure 30. RDAC or EEMEM Random Read
0 WRITE
03824-0-011
1 CMD
S 0 1
0 1 1 A
D
1
A
D
0
0 A C
3
C
2
C
1
C
0
A
2
A
1
A
0
A P
RDAC SLAVE ADDRESS
CMD/
REG
Figure 31. RDAC Quick Command Write (Dummy Write)