Datasheet

AD5253/AD5254 Data Sheet
Rev. C | Page 14 of 32
I
2
C INTERFACE
03824-0-003
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS
S
SCL
SDA
P
Figure 23. I
2
C Interface Timing Diagram
I
2
C INTERFACE GENERAL DESCRIPTION
From Master to Slave
From Slave to Master
S = start condition
P = stop condition
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
R/
W
= read enable at high; write enable at low
R/W A/AS
SLAVE ADDRESS
(7-BIT)
A
0 WRITE
A
INSTRUCTIONS
(8-BIT)
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
DATA
(8-BIT)
P
03824-0-004
Figure 24. I
2
C—Master Writing Data to Slave
R/W AS
SLAVE ADDRESS
(7-BIT)
1 READ
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
DATA
(8-BIT)
DATA
(8-BIT)
P
03824-0-005
AA
Figure 25. I
2
C—Master Reading Data from Slave
R/W R/WS
SLAVE ADDRESS
(7-BIT)
READ OR WRITE (N BYTES +
ACKNOWLEDGE)
SLAVE ADDRESS
DATA
A
S
03824-0-006
REPEATED START READ
OR WRITE
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
A
A/A
(N BYTES +
ACKNOWLEDGE)
DATA
P
A/A
Figure 26. I
2
C—Combined Write/Read