Datasheet

AD5253/AD5254 Data Sheet
Rev. C | Page 12 of 32
–60
–48
–24
–12
0
–36
–54
–30
–18
–6
–42
GAIN (dB)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03824-0-027
0xFF
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 15. Gain vs. Frequency vs. Code, R
AB
= 50 kΩ, T
A
= 25°C
–60
–48
–24
–12
0
–36
–54
–30
–18
–6
–42
GAIN (dB)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03824-0-028
0xFF
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 16. Gain vs. Frequency vs. Code, R
AB
= 100 kΩ, T
A
= 25°C
R
AB
()
CODE (Decimal)
03824-0-029
–100
–80
–60
–40
–20
0
20
40
60
80
100
0 32 64 96 128 160 192 224 256
100k
10k
50k
V
DD
= 5.5V
1k 
Figure 17. ΔR
AB
vs. Code, T
A
= 25°C
CLOCK FREQUENCY (Hz)
03824-0-030
0
0.6
0.4
0.2
0.8
1.0
1.2
1 10010 1k 10k 100k 1M 10M
V
DD
= 2.7V
T
A
= 25°C
V
DD
= 5.5V
I
DD
(mA)
Figure 18. Supply Current vs. Digital Input Clock Frequency
03824-0-031
DIGITAL FEEDTHROUGH
CLK
V
DD
= 5V
V
W
MIDSCALE TRANSITION
7FH  80H
400ns/DIV
Figure 19. Clock Feedthrough and Midscale Transition Glitch
03824-0-046
V
WB0
(0xFF
STORED
IN EEMEM)
V
WB3
(0xFF
STORED
IN EEMEM)
V
DD
= VA0 = VA3 = 3.3V
GND = VB0 = VB3
MIDSCALE
PRESET
RESTORE RDAC0
SETTING TO 0xFF
RESTORE RDAC3
SETTING TO 0xFF
V
DD
(NO DE-
COUPLING
CAPS)
MIDSCALE
PRESET
Figure 20. t
EEMEM_RESTORE
of RDAC0 and RDAC3