Datasheet

AD5251/AD5252 Data Sheet
Rev. D | Page 22 of 28
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and
WP
are digital inputs for which pull-up
resistors are recommended to minimize the MOSFET cross-
conduction current when the driving signals are lower than
V
DD
. SCL and
WP
have ESD protection diodes, as shown in
Figure 35 and Figure 36.
WP
can be permanently tied to V
DD
without a pull-up resistor if
the write-protect feature is not used. If
WP
is left floating, an
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than V
DD
to prevent forward biasing of the diodes.
03823-0-035
GND
S
CL
V
DD
Figure 35. SCL Digital Input
03823-0-036
GND
INPUTS
WP
V
DD
Figure 36. Equivalent
WP
Digital Input
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252 devices
to be operated on one I
2
C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I
2
C programming, each
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1 AD0 Device Addressed
0 0 U1
0 1 U2
1 0 U3
1 1 U4
03823-0-037
5V
R
P
R
P
5V
5V 5V
U1
AD0
AD1
SDA SCL
MASTER
U2
AD0
AD1
SDA SCL
U3
AD0
AD1
SDA SCL
U4
AD0
AD1
SDA
SDA
SCL
SCL
Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Ter minal A, Ter mina l B, or Terminal W th at e xc ee d V
DD
are
clamped by the forward-biased diode. Similarly, negative signals
on Ter mi na l A, Ter minal B, or Term in al W t hat are more
negative than V
SS
are also clamped (see Figure 38). In practice,
users should not operate V
AB
, V
WA
, and V
WB
to be higher than
the voltage across V
DD
to V
SS
, but V
AB
, V
WA
, and V
WB
have no
polarity constraint.
V
SS
V
DD
A
W
B
03823-0-018
Figure 38. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at Termina l A, Te rminal B, and Term inal W ( se e Fig ure 38), it is
important to power on V
DD
/V
SS
before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that V
DD
/V
SS
are powered unintentionally and may affect the
user’s circuit. Similarly, V
DD
/V
SS
should be powered down last.
The ideal power-up sequence is in the following order: GND,
V
DD
, V
SS
, digital inputs, and V
A
/V
B
/V
W
. The order of powering
V
A
, V
B
, V
W
, and the digital inputs is not important, as long as
they are powered after V
DD
/V
SS
.