Datasheet

Data Sheet AD5251/AD5252
Rev. D | Page 15 of 28
I
2
C INTERFACE DETAIL DESCRIPTION
0 WRITE
03823-0-007
S 0 1 0 1 1 A
D
1
A
D
0
0 A A
4
A
3
A
2
A
1
A
0
A P
D
ATA0
(1 BYTE +
ACKNOWLEDGE)
SLA
VE ADDRESS INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
FROM MASTER TO SLAVE
FROM SLA
VE TO MASTER
S = S
TART CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTERACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
Figure 27. Single Write Mode
0 WRITE
03823-0-008
S
0
1
0
1 1
A
D
1
A
D
0
0
A
A
4
A
3
A
2
A
1
A
0
P
A ARDAC1
DATA
RDAC3
DATA
0
(N BYTES +
ACKNOWLEDGE)
RDAC SLAVE ADDRESS
RDAC INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
AX
DATA
Figure 28. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/
W
= 0, CMD/
REG
= 0, EE/
RDAC
= 0)
A4 A3 A2 A1 A0
RDAC Data Byte Description
0 0 0 0 0 Reserved
0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSB of AD5251 are X)
0 0 0 1 0 Reserved
0 0 0 1 1 RDAC3 6-/8-bit wiper setting (2 MSB of AD5251 are X)
0 0 1 0 0 Reserved
: : : : : :
: : : : : :
0 1 1 1 1 Reserved