Datasheet

Data Sheet AD5243/AD5248
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS: ALL VERSIONS
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
1
SCL Clock Frequency f
SCL
0 400 kHz
Bus-Free Time Between Stop and Start, t
BUF
t
1
1.3 μs
Hold Time (Repeated Start), t
HD;STA
t
2
After this period, the first clock pulse is
generated.
0.6 μs
Low Period of SCL Clock, t
LOW
t
3
1.3 μs
High Period of SCL Clock, t
HIGH
t
4
0.6 μs
Setup Time for Repeated Start Condition, t
SU;STA
t
5
0.6 μs
Data Hold Time, t
HD;DAT
2
t
6
0.9 μs
Data Setup Time, t
SU;DAT
t
7
100 ns
Fall Time of Both SDA and SCL Signals, t
F
t
8
300 ns
Rise Time of Both SDA and SCL Signals, t
R
t
9
300 ns
Setup Time for Stop Condition, t
SU;STO
t
10
0.6 μs
1
See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).
2
The maximum t
HD:DAT
must be met only if the device does not stretch the low period (t
LOW
) of the SCL signal.
04109-0-021
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS
S
SCL
SDA
P
Figure 3. I
2
C Interface Detailed Timing Diagram