Datasheet

Data Sheet AD5247
Rev. F | Page 5 of 20
Parameter Symbol Conditions Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
6, 8
Bandwidth 3 dB BW R
AB
= 10 kΩ/50 kΩ/100 kΩ,
code = 0x40
600/100/40
kHz
Total Harmonic Distortion THD
W
V
A
=1 V rms, f = 1 kHz, R
AB
= 10 kΩ 0.05 %
V
W
Settling Time (10 kΩ/50 kΩ/100 kΩ) t
S
V
A
= 5 V ±1 LSB error band 2 µs
Resistor Noise Voltage Density e
N_WB
R
WB
= 5 kΩ, R
S
= 0 9 nV/√Hz
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W,
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design, not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
TIMING CHARACTERISTICS5 kΩ, 10 kΩ, 50 k, AND 100 kΩ VERSIONS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
, −40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter
1, 2, 3
Symbol
Min
Typ
4
Max
Unit
SCL Clock Frequency f
SCL
400 kHz
Bus Free Time Between Stop and Start, t
BUF
t
1
1.3
µs
Hold Time (Repeated Start), t
HD;STA
5
t
2
0.6 µs
Low Period of SCL Clock, t
LOW
t
3
1.3 µs
High Period of SCL Clock, t
HIGH
t
4
0.6 50 µs
Setup Time for Repeated Start Condition, t
SU;STA
t
5
0.6 µs
Data Hold Time, t
HD;DAT
t
6
0.9 µs
Data Setup Time, t
SU;DAT
t
7
100 ns
Fall Time of Both SDA and SCL Signals, t
F
t
8
300 ns
Rise Time of Both SDA and SCL Signals, t
R
t
9
300 ns
Setup Time for Stop Condition, t
SU;STO
t
10
0.6 µs
1
Specifications apply to all parts.
2
Guaranteed by design, not subject to production test.
3
See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.
4
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
5
After this period, the first clock pulse is generated.
t
7
t
8
t
9
P S
P
S
t
10
t
5
t
9
t
8
SCL
SDA
t
6
03876-031
t
1
t
2
t
3
t
4
t
2
Figure 2. I
2
C Interface, Detailed Timing Diagram