Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- I2C Interface
- Theory of Operation
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- I2C-Compatible 2-Wire Serial Bus
- Level Shifting for Bidirectional Interface
- ESD Protection
- Terminal Voltage Operating Range
- Maximum Operating Current
- Power-Up Sequence
- Layout and Power Supply Bypassing
- Constant Bias to Retain Resistance Setting
- Outline Dimensions

AD5247 Data Sheet
Rev. F | Page 16 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems can be operated at one voltage, a
new component can be optimized at another voltage. When
two systems operate the same signal at two different voltages,
proper level shifting is needed. For instance, users can employ
a 3.3 V E
2
PROM to interface with a 5 V digital potentiometer. A
level shifting scheme is needed to enable a bidirectional commu-
nication so that the setting of the digital potentiometer can be
stored in and retrieved from the E
2
PROM. Figure 36 shows one
of the level-shifting implementations. M1 and M2 can be any
N-channel signal FETs, or if V
DD
falls below 2.5 V, M1 and M2
can be low threshold FETs such as the FDV301N.
E
2
PROM
AD5247
SDA1
SCL1
D
G
R
P
R
P
3.3V
5V
S
M1
SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V V
DD2
=
5V
D
03876-035
Figure 36. Level-Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures as shown in Figure 37. This applies
to digital input pins (SDA and SCL).
340Ω
GND
03876-036
LOGIC
SDA/
SCL
Figure 37. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A and Terminal W that exceed
V
DD
or GND are clamped by the internal forward biased diodes
(see Figure 38).
A
V
DD
W
GND
03876-038
Figure 38. Maximum Terminal Voltages Set by V
DD
and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that, due to low
resistance values, the current through the RDAC might exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through Terminal W and Terminal B is plotted
with respect to code. A line is also drawn denoting the 5 mA
current limit. Note that at low code values (particularly for the
5 kΩ and 10 kΩ options), the current level increases signifi-
cantly. Care should be taken to limit the current flow between
W and B in this state to a maximum continuous current of
5 mA and a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contacts can occur.
CODE (Decimal)
I
WB
CURRENT (mA)
0
0.01
0.1
1
10
16 32 48
64 80 96 112 128
100
5mA CURRENT LIMIT
R
AB
= 5kΩ
R
AB
= 10kΩ
R
AB
= 100kΩ
R
AB
= 50kΩ
03876-039
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A and Terminal W (see Figure 38), it is important
to power V
DD
/GND before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that V
DD
is powered unintentionally and can affect the rest of the
user’s circuit. The ideal power-up sequence is in the following
order: GND, V
DD
, digital inputs, V
A
, and V
W
. The relative order
of powering V
A
and V
W
and the digital inputs is not important
as long as they are powered after V
DD
/GND.