Datasheet

Data Sheet AD5246
Rev. C | Page 5 of 16
TIMING CHARACTERISTICS
V
DD
= 5 V ± 10% or 3 V ± 10%; V
A
= V
DD
; –40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
1
Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
2, 3, 4
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time Between STOP and START t
1
1.3 µs
t
HD;STA
Hold Time (Repeated START) t
2
After this period, the first clock pulse is
generated
0.6 µs
t
LOW
Low Period of SCL Clock t
3
1.3 µs
t
HIGH
High Period of SCL Clock t
4
0.6 50 µs
t
SU;STA
Setup Time for Repeated START Condition t
5
0.6 µs
t
HD;DAT
Data Hold Time t
6
0.9 µs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for STOP Condition t
10
0.6 µs
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design; not subject to production test.
3
See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values.
4
Specifications apply to all parts.