Datasheet
Data Sheet AD5246
Rev. C | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
V
DD
= 5 V ± 10% or 3 V ± 10%; V
A
= +V
DD
; –40°C < T
A
< +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ
1
Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
WB
–1.5 ±0.1 +1.5 LSB
Resistor Integral Nonlinearity
2
R-INL R
WB
–4 ±0.75 +4 LSB
Nominal Resistor Tolerance
3
∆R
AB
T
A
= 25°C
–30
+30
%
Resistance Temperature Coefficient (∆R
AB
/R
AB
)/∆T Wiper = no connect 45 ppm/°C
R
WB
R
WB
Code = 0x00, V
DD
= 5 V 75 150 Ω
Code = 0x00, V
DD
= 2.7 V 150 400 Ω
RESISTOR TERMINALS
Voltage Range
4
V
B, W
GND V
DD
V
Capacitance
5
B C
B
f = 1 MHz, measured to GND, code = 0x40 45 pF
Capacitance
5
W C
W
f = 1 MHz, measured to GND, code = 0x40 60 pF
Common-Mode Leakage I
CM
1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
V
DD
= 5 V 2.4 V
Input Logic Low
V
IL
V
DD
= 5 V
0.8
V
Input Logic High V
IH
V
DD
= 3 V 2.1 V
Input Logic Low V
IL
V
DD
= 3 V 0.6 V
Input Current I
IL
V
IN
= 0 V or 5 V ±1 µA
Input Capacitance
5
C
IL
5 pF
POWER SUPPLIES
Power Supply Range V
DD RANGE
2.7 5.5 V
Supply Current I
DD
V
DD
= 5.5 V; V
IH
= V
DD
or V
IL
= GND 3 7 µA
V
DD
= 5 V; V
IH
= V
DD
or V
IL
= GND 2.5 5.2 µA
V
DD
= 3.3 V; V
IH
= V
DD
or V
IL
= GND 0.9 2 µA
Power Dissipation
6
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V 40 µW
Power Supply Sensitivity PSSR V
DD
= +5 V ± 10%, code = midscale ±0.01 ±0.025 %/%
DYNAMIC CHARACTERISTICS
5, 7
Bandwidth –3 dB BW_5K R
AB
= 5 kΩ, code = 0x40 1.2 MHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz 0.05 %
V
W
Settling Time t
S
V
A
= 5 V, ±1 LSB error band 1 µs
Resistor Noise Voltage Density e
N_WB
R
WB
= 2.5 kΩ, R
S
= 0 Ω 6 nV/√Hz
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
Code = 0x7F.
4
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design; not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
V
DD
= 5 V.