Datasheet

AD5246 Data Sheet
Rev. C | Page 12 of 16
I
2
C INTERFACE
Table 6. Write Mode
S 0 1 0 1 1 1 0
W
A X D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
Table 7. Read Mode
S 0 1 0 1 1 1 0 R A 0 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
S = Start Condition.
P = Stop Condition.
A = Acknowledge.
X = Don’t Care.
W
= Write.
R = Read.
D6, D5, D4, D3, D2, D1, D0 = Data Bits.
t
1
t
3
t
4
t
2
t
7
t
8
t
9
P S
P
S
t
10
t
5
t
9
t
8
SCL
SDA
t
2
t
6
03875-019
Figure 26. I
2
C Interface, Detailed Timing Diagram
SCL
FRAME 1
FRAME 2
START BY
MASTER
ACK BY
AD5246
SLAVE ADDRESS BYTE
STOP BY
MASTER
DATA BYTE
SDA
0
1
0
1
1 1 0 R/W
X D6 D4 D3 D2 D1 D0
1
1 9
ACK BY
AD5246
19
D5
03875-014
Figure 27. Writing to the RDAC Register
NO ACK
BY MASTER
SCL
SDA
0
1 0 1 1 1 0 R/W
0
D6 D5 D4 D3 D2 D1 D0
1
919
FRAME 1
FRAME 2
START BY
MASTER
ACK BY
AD5246
SLAVE ADDRESS BYTE
RDAC REGISTER
STOP BY
MASTER
03875-013
Figure 28. Reading from the RDAC Register