Datasheet

AD5245
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS
5 KΩ, 10 KΩ, 50 KΩ, 100 KΩ VERSIONS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
, V
B
= 0 V, –40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
1
Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
2, , 3 4
(Specifications Apply to All Parts)
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time Between STOP and START t
1
1.3 µs
t
HD;STA
Hold Time (Repeated START) t
2
After this period, the first clock
pulse is generated.
0.6 µs
t
LOW
Low Period of SCL Clock t
3
1.3 µs
t
HIGH
High Period of SCL Clock t
4
0.6 µs
t
SU;STA
Setup Time for Repeated START Condition t
5
0.6 µs
t
HD;DAT
Data Hold Time t
6
0.9 µs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for STOP Condition t
10
0.6 µs
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design and not subject to production test.
3
See timing diagram ( ) for locations of measured values. Figure 44
4
Standard I
2
C mode operation guaranteed by design.