Datasheet

AD5241/AD5242
Rev. C | Page 5 of 20
TIMING DIAGRAMS
t
8
t
1
t
8
t
3
t
2
t
2
t
9
t
5
S
D
A
SCL
t
10
S P
t
7
t
4
SP
t
6
0
0926-005
Figure 3. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I
2
C bus in the following serial format.
Table 2.
S 0 1 0 1 1 AD1 AD0
R/
W
A
A
/B
RS SD O
1
O
2
X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/
W
= Read enable at high and output to SDA. Write enable at low.
A
/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as
SHDN
except inverse logic.
O
1
, O
2
= Output logic pin latched values
D7, D6, D5, D4, D3, D2, D1, D0 = data bits.
1 119 99
0
1
0
1
A/B D0D4D5D6D7 D3 D2 D1
ACK BY
AD5241
ACK BY
AD5241
ACK BY
AD5241
STOP BY
MASTER
S
TART BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
SDA
1
AD1 AD0
R/W
SCL
XXX
21
SDRS
00926-006
OO
Figure 4. Writing to the RDAC Serial Register
1
919
0
1
0
11
D7
ACK BY
AD5241
NO ACK BY
MASTER
STOP BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
RDAC REGISTER IN WRITE MODE
SCL
SDA
D6 D5 D4 D3 D2 D1 D0
AD1 AD0
R/W
0
0926-007
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode