Datasheet

AD5241/AD5242
Rev. C | Page 4 of 20
Parameter Symbol Conditions Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
5, 7, 8
−3 dB Bandwidth BW_10 kΩ R
AB
= 10 kΩ, code = 0x80 650 kHz
BW_100 kΩ R
AB
= 100 kΩ, code = 0x80 69 kHz
BW_1 MΩ R
AB
= 1 MΩ, code = 0x80 6 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms + 2 V dc,
V
B
= 2 V dc, f = 1 kHz
0.005 %
V
W
Settling Time t
S
V
A
= V
DD
, V
B
= 0 V, ± 1 LSB
error band, R
AB
= 10 kΩ
2 μs
Resistor Noise Voltage e
N_WB
R
WB
= 5 kΩ, f = 1 kHz 14 nV√Hz
INTERFACE TIMING CHARACTERISTICS
(APPLIES TO ALL PARTS
5, 9
)
SCL Clock Frequency f
SCL
0 400 kHz
Bus Free Time Between Stop and Start, t
BUF
t
1
1.3 μs
Hold Time (Repeated Start), t
HD; STA
t
2
After this period, the first
clock pulse is generated
600 ns
Low Period of SCL Clock, t
LOW
t
3
1.3 μs
High Period of SCL Clock, t
HIGH
t
4
0.6 50 μs
Setup Time for Repeated Start Condition, t
SU; STA
t
5
600 ns
Data Hold Time, t
HD; DAT
t
6
900 ns
Data Setup Time, t
SU; DAT
t
7
100 ns
Rise Time of Both SDA and SCL Signals, t
R
t
8
300 ns
Fall Time of Both SDA and SCL Signals, t
F
t
9
300 ns
Setup Time for Stop Condition, t
SU; STO
t
10
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.
4
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design, not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
DD
= 5 V.
9
See timing diagram in Figure 3 for location of measured values.