Datasheet
Data Sheet AD5235
Rev. F | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDI
SDO
GND
A1
V
SS
W1
CLK
B1
CS
PR
WP
V
DD
A2
02816-005
W2
B2
RDY
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5235
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
4
GND
Ground Pin, Logic Ground Reference.
5 V
SS
Negative Supply. Connect to 0 V for single-supply applications. If V
SS
is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 V
DD
Positive Power Supply.
13
WP
Optional Write Protect. When active low,
WP
prevents any changes to the present contents, except
PR
strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie
WP
to V
DD
, if not used.
14
PR
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale until EEMEM is loaded with a new value by the user.
PR
is activated
at the logic high transition. Tie
PR
to V
DD
, if not used.
15
CS
Serial Register Chip Select Active Low. Serial register operation takes place when
CS
returns to logic high.
16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and
PR
.