Datasheet

Data Sheet AD5235
Rev. F | Page 19 of 32
In Table 6, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.
Table 6. 24-Bit Serial Data-Word
MSB
Command Byte 0
Data Byte 1
Data Byte 0
LSB
RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command instruction codes are defined in Table 7.
Table 7. Command Operation Truth Table
1, 2, 3
Command
Number
Command Byte 0 Data Byte 1 Data Byte 0
Operation
B23 B16 B15 B8 B7 B0
C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0
0 0 0 0 0 X X X X X … X X X … X
NOP. Do nothing. See
Table 19
1 0 0 0 1 0 0 0 A0 X … X X X … X
Restore EEMEM (A0) contents to RDAC (A0)
register. See Table 16.
2 0 0 1 0 0 0 0 A0 X … X X X … X
Store wiper setting. Store RDAC (A0) setting to
EEMEM (A0). See
Table 15.
3
4
0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0
Store contents of Serial Register Data Byte 0
and Serial Register Data Bytes 1 (total 16 bits)
to EEMEM (ADDR). See
Table 18.
4
5
0 1 0 0 0 0 0 A0 X … X X X … X
Decrement by 6 dB. Right-shift contents of
RDAC (A0) register, stop at all 0s.
5
5
0 1 0 1 X X X X X … X X X … X
Decrement all by 6 dB. Right-shift contents of
all RDAC registers, stop at all 0s.
6
5
0
1
1
0
0
0
0
A0
X
…
X
X
X
…
X
Decrement contents of RDAC (A0) by 1,
stop at all 0s.
7
5
0
1
1
1
X
X
X
X
X
…
X
X
X
…
X
Decrement contents of all RDAC registers by 1,
stop at all 0s.
8 1 0 0 0 0 0 0 0 X … X X X … X
Reset. Refresh all RDACs with their corresponding
EEMEM previously stored values.
9 1 0 0 1 A3 A2 A1 A0 X … X X X … X
Read contents of EEMEM (ADDR) from
SDO output in the next frame. See
Table 19.
10 1 0 1 0 0 0 0 A0 X … X X X … X
Read RDAC wiper setting from SDO output
in the next frame. See
Table 20.
11 1 0 1 1 0 0 0 A0 X … D9 D8 D7 … D0
Write contents of Serial Register Data Byte 0
and Serial Register Data Byte 1 (total 10 bits)
to RDAC (A0). See
Table 14.
12
5
1 1 0 0 0 0 0 A0 X … X X X … X
Increment by 6 dB: Left-shift contents of RDAC
(A0), stop at all 1s. See
Table 17.
13
5
1 1 0 1 X X X X X … X X X … X
Increment all by 6 dB. Left-shift contents of
all RDAC registers, stop at all 1s.
14
5
1 1 1 0 0 0 0 A0 X … X X X … X
Increment contents of RDAC (A0) by 1,
stop at all 1s. See
Table 15.
15
5
1 1 1 1 X X X X X … X X X … X
Increment contents of all RDAC registers by 1,
stop at all 1s.
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a
full 24-bit data-word to completely clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the
CS
strobe returns to logic high.
4
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1.