Datasheet

AD5233
Rev. B | Page 18 of 32
In Table 6, C0 to C3 are command bits, A3 to A0 are address bits, D0 to D5 are data bits that are applicable to the RDAC wiper register,
and D0 to D7 are applicable to the EEMEM register.
Table 6. 16-Bit Serial Data-Word
MSB Instruction Byte LSB Data Byte
RDAC C3 C2 C1 C0 0 0 A1 A0 X X D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Command instruction codes are defined in Table 7.
Table 7. Instruction/Operation Truth Table
1, 2, 3
Inst.
No.
Instruction Byte 0 Data Byte 0
Operation
B16 B8 B7 B6 B5 B4 B3 B2 B1 B0
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 X X X X X X X X X X X X NOP: Do nothing. See Table 14 for
programming example.
1 0 0 0 1 0 0 A1 A0 X X X X X X X X Restore EEMEM contents to the RDAC
register. This command leaves the device
in read program power state. To return
the part to the idle state, perform NOP
instruction 0. See Table 14.
2 0 0 1 0 0 0 A1 A0 X X X X X X X X Store wiper setting: Store RDAC (ADDR)
setting to EEMEM. See Table 13.
3
4
0 0 1 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Store contents of Serial Register Data
Byte 0 (total eight bits) to EEMEM
(ADDR). See Table 16.
4
5
0 1 0 0 0 0 A1 A0 X X X X X X X X Decrement 6 dB: right-shift contents of
RDAC register, stop at all 0s.
5
5
0 1 0 1 X X X X X X X X X X X X Decrement all 6 dB: right-shift contents
of all RDAC registers, stop at all 0s.
6
5
0 1 1 0 0 0 A1 A0 X X X X X X X X Decrement content of RDAC register
by 1, stop at all 0s.
7
5
0 1 1 1 X X X X X X X X X X X X Decrement contents of all the RDAC
registers by 1, stop at all 0s.
8 1 0 0 0 X X X X X X X X X X X X Reset: refresh all RDACs with their
corresponding EEMEM previously
stored values.
9 1 0 0 1 A3 A2 A1 A0 X X X X X X X X Read content of EEMEM (ADDR) from
SDO output in the next frame. See
Table 17.
10 1 0 1 0 0 0 A1 A0 X X X X X X X X Read RDAC wiper setting from SDO
output in the next frame. See Table 18.
11 1 0 1 1 0 0 A1 A0 X X D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data
Byte 0 (total six bits) to RDAC. See
Table 12.
12
5
1 1 0 0 0 0 A1 A0 X X X X X X X X Increment 6 dB: Left-shift contents of
RDAC register, stop at all 1s. See
Table 15.
13
5
1 1 0 1 X X X X X X X X X X X X Increment all 6 dB: left-shift contents of
RDAC registers, stop at all 1s.
14
5
1 1 1 0 0 0 A1 A0 X X X X X X X X Increment contents of the RDAC
register by 1, stop at all 1s. See
Table 13.
15
5
1 1 1 1 X X X X X X X X X X X X Increment contents of all RDAC
registers by 1, stop at all 1s.
1
The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, see details of these instructions for proper usage.
2
The RDAC register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the
CS
strobe returns to Logic 1.
4
Instruction 3 writes one data byte (eight bits of data) to EEMEM. In the case of Address 0, Address 1, Address 2, and Address 3, only the last six bits are valid for wiper
position setting.
5
The increment, decrement, and shift instructions ignore the contents of the Shift Register Data Byte 0.