Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- Theory of Operation
- Scratch Pad and EEMEM Programming
- Basic Operation
- EEMEM Protection
- Digital Input/Output Configuration
- Serial Data Interface
- Daisy-Chaining Operation
- Advanced Control Modes
- Using Additional Internal, Nonvolatile EEMEM
- Terminal Voltage Operating Range
- Detailed Potentiometer Operation
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- Operation from Dual Supplies
- Application Programming Examples
- Equipment Customer Start-up Sequence for a PCB Calibrated Unit with Protected Settings
- Flash/EEMEM Reliability
- Evaluation Board
- Outline Dimensions

Data Sheet AD5232
Rev. C | Page 5 of 24
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V
DD
= 3 V and V
DD
= 5 V.
Table 2.
Parameter
1, 2
Symbol Conditions Min Typ
3
Max Unit
Clock Cycle Time (t
CYC
) t
1
20 ns
CS
Setup Time t
2
10 ns
CLK Shutdown Time to
CS
Rise t
3
1 t
CYC
Input Clock Pulse Width t
4
, t
5
Clock level high or low 10 ns
Data Setup Time
t
6
From positive CLK transition
5
ns
Data Hold Time t
7
From positive CLK transition 5 ns
CS
to SDO-SPI Line Acquire t
8
40 ns
CS
to SDO-SPI Line Release t
9
50 ns
CLK to SDO Propagation Delay
4
t
10
R
P
= 2.2 kΩ, C
L
< 20 pF 50 ns
CLK to SDO Data Hold Time t
11
R
P
= 2.2 kΩ, C
L
< 20 pF 0 ns
CS
High Pulse Width
5
t
12
10 ns
CS
High to
CS
High
5
t
13
4 t
CYC
RDY Rise to
CS
Fall t
14
0 ns
CS
Rise to RDY Fall Time t
15
0.15 0.3 ms
Store/Read EEMEM Time
6
t
16
Applies to Command Instruction 2, Command
Instruction 3, and Command Instruction 9
25 ms
CS
Rise to Clock Rise/Fall Setup t
17
10 ns
Preset Pulse Width (Asynchronous) t
PRW
Not shown in timing diagram 50 ns
Preset Response Time to RDY High t
PRESP
PR
pulsed low to refresh wiper positions
70 µs
1
Guaranteed by design; not subject to production test.
2
See the Timing Diagrams section for the location of measured values.
3
Typicals represent average readings at 25°C and V
DD
= 5 V.
4
Propagation delay depends on the value of V
DD
, R
PULL-UP
, and C
L
.
5
Valid for commands that do not activate the RDY pin.
6
RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the
PR
hardware pulse:
CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at T
A
= −40°C and V
DD
< 3 V extends the save time to 35 ms.