Datasheet

Data Sheet AD5231
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
V
DD
= 3 V to 5.5 V, V
SS
= 0 V, and −40°C < T
A
< +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS
2, 3
Clock Cycle Time (t
CYC
) t
1
20 ns
CS Setup Time
t
2
10 ns
CLK Shutdown Time to CS Rise
t
3
1 t
CYC
Input Clock Pulse Width t
4
, t
5
Clock level high or low 10 ns
Data Setup Time t
6
From positive CLK transition 5 ns
Data Hold Time t
7
From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire
t
8
40 ns
CS to SDO-SPI Line Release
t
9
50 ns
CLK to SDO Propagation Delay
4
t
10
R
P
= 2.2 kΩ, C
L
< 20 pF 50 ns
CLK to SDO Data Hold Time t
11
R
P
= 2.2 kΩ, C
L
< 20 pF 0 ns
CS High Pulse Width
5
t
12
10 ns
CS High to CS High
5
t
13
4 t
CYC
RDY Rise to CS Fall
t
14
0 ns
CS Rise to RDY Fall Time
t
15
0.1 0.15 ms
Store/Read EEMEM Time
6
t
16
Applies to instructions 0x2, 0x3, and 0x9 25 ms
Power-On EEMEM Restore Time t
EEMEM1
R
AB
= 10 kΩ 140 μs
Dynamic EEMEM Restore Time t
EEMEM2
R
AB
= 10 kΩ 140 μs
WP High or Low to CS Fall Time
t
WP
40 ns
CS Rise to Clock Rise/Fall Setup
t
17
10 ns
Preset Pulse Width (Asynchronous) t
PRW
Not shown in timing diagram 50 ns
Preset Response Time to Wiper Setting t
PRESP
PR
pulsed low to refresh wiper positions
70 μs
FLASH/EE MEMORY RELIABILITY
Endurance
7
100 kCycles
Data Retention
8
100 Years
1
Typical values represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design and not subject to production test.
3
See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V. Switching characteristics are measured using both V
DD
= 3 V and V
DD
= 35 V.
4
Propagation delay depends on the value of V
DD
, R
PULL-UP
, and C
L
.
5
Valid for commands that do not activate the RDY pin.
6
RDY pin low only for Instructions 2, 3, 8, 9, 10, and the
PR
hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at T
A
= −40°C and
V
DD
< 3 V extends the EEMEM store time to 35 ms.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
8
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.