Datasheet

Data Sheet AD5231
Rev. D | Page 17 of 28
In Table 6, command bits are C0 to C3, address bits are A3 to A0, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.
Table 6. AD5231 24-Bit Serial Data-Word
MSB Command Byte 0
Data Byte 1
Data Byte 0
LSB
RDAC C3 C2 C1 C0 0 0 0 0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Command instruction codes are defined in Table 7.
Table 7. Command/Operation Truth Table
1, 2, 3
Instruction
Number
Command Byte 0 Data Byte 1 Data Byte 0
Operation
B23 B16 B15 B8 B7 B0
C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0
0 0 0 0 0 X X X X X … X X X … X NOP: Do nothing. See Table 15.
1 0 0 0 1 0 0 0 0 X … X X X … X
Restore EEMEM(0) contents to RDAC register.
This command leaves the device in the read
program power state. To return the part to
the idle state, perform NOP instruction 0. See
Table 15.
2 0 0 1 0 0 0 0 0 X … X X X … X
Store Wiper Setting: Store RDAC setting to
EEMEM(0). See Table 14.
3
4
0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0
Store contents of Data Bytes 0 and 1 (total
16 bits) to EEMEM (ADDR 1to ADDR 15). See
Table 17.
4
5
0 1 0 0 0 0 0 0 X … X X X … X Decrement RDAC by 6 dB.
5
5
0 1 0 1 X X X X X … X X X … X Same as Instruction 4.
6
5
0 1 1 0 0 0 0 0 X … X X X … X Decrement RDAC by 1 position.
7
5
0 1 1 1 X X X X X … X X X … X Same as Instruction 6.
8 1 0 0 0 X X X X X … X X X … X Reset: Restore RDAC with EEMEM (0) value.
9 1 0 0 1 A3 A2 A1 A0 X … X X X … X
Read EEMEM (ADDR 0 to ADDR 15) from SDO
output in the next frame. See Table 18.
10
1
0
1
0
0
0
0
0
X
…
X
X
X
…
X
Read RDAC wiper setting from SDO output
in the next frame. See Table 19.
11 1 0 1 1 0 0 0 0 X … D9 D8 D7 … D0
Write contents of Data Bytes 0 and 1 (total
10 bits) to RDAC. See Table 13.
12
5
1 1 0 0 0 0 0 0 X … X X X … X Increment RDAC by 6 dB. See Table 16.
13
5
1 1 0 1 X X X X X … X X X … X Same as Instruction 12.
14
5
1 1 1 0 0 0 0 0 X … X X X … X Increment RDAC by 1 position. See Table 14.
15
5
1 1 1 1 X X X X X … X X X … X Same as Instruction 14.
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instruction following 9 and 10 must also be a full 24-bit data-word to
completely clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the
CS
strobe returns to logic high.
4
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift instructions ignore the contents of the shift register Data Byte 0 and Data Byte 1.