Datasheet

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Nonvolatile Memory,

1024-Position Digital Potentiometer

Data Sheet

AD5231

Rev. D

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FEATURES

1024-position resolution

Nonvolatile memory maintains wiper setting

Power-on refresh with EEMEM setting

EEMEM restore time: 140 µs typ

Full monotonic operation

10 kΩ, 50 kΩ, and 100 kΩ terminal resistance

Permanent memory write protection

Wiper setting readback

Predefined linear increment/decrement instructions

Predefined ±6 dB/step log taper increment/decrement

instructions

SPI®-compatible serial interface

3 V to 5 V single-supply or ±2.5 V dual-supply operation

28 bytes extra nonvolatile memory for user-defined data

100-year typical data retention, T

= 55°C

APPLICATIONS

Mechanical potentiometer replacement

Instrumentation: gain, offset adjustment

Programmable voltage to current conversion

Programmable filters, delays, time constants

Programmable power supply

Low resolution DAC replacement

Sensor calibration

FUNCTIONAL BLOCK DIAGRAM

EEMEM(0)

EEMEM(1)

AD5231

RDAC

CLK

SDI

GND

SDO

RDY

SDO

SDI

ADDR

DECODE

RDAC

DIGITAL

SERIAL

INTERFACE

EEMEM

CONTROL

28 BYTES

USER EEMEM

DIGITAL

OUTOUT

BUFFER

02739-001

Figure 1.

CODE (Decimal)

100

0 1023256

(D), R

(D); (% of Nominal R

)

512 768

02739-002

Figure 2. R

(D) and R

(D) vs. Decimal Code

GENERAL DESCRIPTION

The AD5231 is a nonvolatile memory

, digitally controlled

potentiometer

with 1024-step resolution. The device performs

the same electronic adjustment function as a mechanical

potentiometer with enhanced resolution, solid state reliability,

and remote controllability. The AD5231 has versatile programming

that uses a standard 3-wire serial interface for 16 modes of

operation and adjustment, including scratchpad programming,

memory storing and restoring, increment/decrement, ±6 dB/step

log taper adjustment, wiper setting readback, and extra EEMEM

for user-defined information, such as memory data for other

components, look-up table, or system identification information.

In scratchpad programming mode, a specific setting can be

programmed directly to the RDAC register that sets the

resistance between Terminals W–A and Terminals W–B. This

setting can be stored into the EEMEM and is transferred

automatically to the RDAC register during system power-on.

The EEMEM content can be restored dynamically or through

external

strobing, and a

function protects EEMEM

contents. To simplify the programming, the linear-step increment

or decrement commands can be used to move the RDAC wiper

up or down, one step at a time. The ±6 dB step commands can

be used to double or half the RDAC wiper setting.

The AD5231 is available in a 16-lead TSSOP. The part is

guaranteed to operate over the extended industrial temperature

range of −40°C to +85°C.

The terms nonvolatile memory and EEMEM are used interchangeably.

The terms digital potentiometer and RDAC are used interchangeably.

Summary of content (28 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM AD5231 CS ADDR DECODE CLK RDAC REGISTER A SDI SDI W SERIAL INTERFACE GND SDO SDO WP EEMEM(0) DIGITAL REGISTER O1 2 EEMEM CONTROL RDY B DIGITAL OUTOUT BUFFER VSS PR Figure 1.
PAGE 2
AD5231 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Latched Digital Outputs ............................................................ 16 Applications ....................................................................................... 1 Advanced Control Modes ......................................................... 18 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD5231 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. Table 1.
PAGE 4
AD5231 Parameter POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Data Sheet Symbol Conditions Min VDD VDD/VSS IDD ISS VSS = 0 V 2.7 ±2.
PAGE 5
Data Sheet AD5231 TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted. Table 2.
PAGE 6
AD5231 Data Sheet Timing Diagrams CPHA = 1 t12 CS t3 t13 t1 t2 t5 CLK CPOL = 1 B23 B0 t17 t4 t7 t6 HIGH OR LOW B23–MSB t8 t11 t10 B23–MSB B24* SDO HIGH OR LOW B0–LSB t9 B0–LSB t14 t15 t16 RDY * NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. 02739-003 SDI Figure 3.
PAGE 7
Data Sheet AD5231 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameters VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND A–B, A–W, B–W Intermittent 1 Continuous Digital Input and Output Voltage to GND Operating Temperature Range 2 Maximum Junction Temperature (TJ max) Storage Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance Junction-to-Ambient (θJA),TSSOP-16 Junction-to-Case (θJC), TSSOP-16 Package Power Dissipation Ratings –0.
PAGE 8
AD5231 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS O1 1 16 O2 CLK 2 15 RDY 14 CS SDI 3 GND 5 AD5231 13 PR TOP VIEW (Not to Scale) 12 WP VSS 6 11 VDD T 7 10 A B 8 9 W 02739-005 SDO 4 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic O1 2 3 4 CLK SDI SDO 5 6 GND VSS 7 8 9 10 11 12 T B W A VDD WP 13 PR 14 15 16 CS RDY O2 Description Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0.
PAGE 9
Data Sheet AD5231 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 2.0 VDD = 5V, VSS = 0V TA = +85°C 1.5 1.0 TA = –40°C R-DNL (LSB) INL ERROR (LSB) 1.0 0.5 TA = +25°C 0 0.5 0 –0.5 TA = +25°C TA = +85°C TA = –40°C –1.0 –0.5 0 128 384 256 640 512 768 896 1024 CODE (Decimal) –2.0 02739-006 –1.0 0 640 512 384 CODE (Decimal) 768 896 1024 3000 2.0 VDD = 5.5V, VSS = 0V TA = –40°C TO +85°C VDD = 5V, VSS = 0V TA = –40°C 0.5 0 –0.5 TA = +85°C TA = +25°C –1.0 –2.
PAGE 10
AD5231 Data Sheet 2 60 VDD = 2.7V, VSS = 0V TA = 25°C f–3dB = 37kHz, RAB = 10kΩ 0 50 –2 –4 GAIN (dB) RW (Ω) 40 30 f–3dB = 44kHz, RAB = 100kΩ –6 f–3dB = 85kHz, RAB = 50kΩ –8 –10 20 –12 10 128 0 384 256 640 512 768 896 1024 CODE (Decimal) –16 1k 02739-012 0 Figure 12. Wiper On Resistance vs. Code 10k 100k FREQUENCY (Hz) 1M 02739-015 VA = 1mV rms VDD/VSS = ±2.5V D = MIDSCALE –14 Figure 15. −3 dB Bandwidth vs. Resistance (Figure 32) 4 0.12 VDD/VSS = ±2.5V VA = 1V rms 0.
PAGE 11
Data Sheet AD5231 0 CODE = 0x200 VDD = 5V VA = 2.25V VB = 0V 100 –10 0x100 VA 90 0x80 –20 GAIN (dB) 0x40 –30 VW 0x20 EXPECTED VALUE 0x10 –40 0x08 MIDSCALE 0x04 0.5V/DIV 0x02 10 0% –60 1k 10k 1M 100k FREQUENCY (Hz) 02739-018 0x01 Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 32) 100µs/DIV Figure 21. Power-On Reset, VA = 2.25 V, VB = 0 V, Code = 1010101010B 0 2.55 VDD/VSS = 5V/0V CODE = 0x200 TO 0x1FF CODE = 0x200 –10 02739-021 –50 0x100 2.
PAGE 12
AD5231 Data Sheet 100 VA = VB = OPEN TA = 25°C 5V/DIV THEORETICAL—IWB_MAX (mA) CS CLK 5V/DIV SDI 5V/DIV 10 RAB = 10kΩ 1 RAB = 50kΩ 0.1 RAB = 100kΩ 0.01 0 *SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION 0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM). 02739-024 4ms/DIV Figure 24. IDD vs. Time when Restoring Data from EEMEM 128 256 384 512 640 CODE (Decimal) Figure 25. IWB_MAX vs. Code Rev.
PAGE 13
Data Sheet AD5231 TEST CIRCUITS Figure 26 to Figure 35 define the test conditions used in the specifications. 5V NC DUT A W IW OP279 VIN OFFSET GND Figure 26. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT B W DUT OP42 B OFFSET GND 02739-027 VMS +15V A VIN W V+ +2.5V Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 32. Gain vs. Frequency W RSW = DUT A W IW VW 0.
PAGE 14
AD5231 Data Sheet THEORY OF OPERATION The AD5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to VDD − VSS < 5.5 V. The digital potentiometer wiper position is determined by the RDAC register contents.
PAGE 15
Data Sheet AD5231 DIGITAL INPUT/OUTPUT CONFIGURATION All digital inputs are ESD-protected, high input impedance that can be driven directly from most digital sources. Active at logic low, PR and WP must be tied to VDD if they are not used. No internal pull-up resistors are present on any digital input pins. The SDO and RDY pins are open-drain digital outputs that need pull-up resistors only if these functions are used.
PAGE 16
AD5231 Data Sheet TERMINAL VOLTAGE OPERATION RANGE POWER-UP SEQUENCE The AD5231’s positive VDD and negative VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 40).
PAGE 17
Data Sheet AD5231 In Table 6, command bits are C0 to C3, address bits are A3 to A0, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are applicable to EEMEM. Table 6. AD5231 24-Bit Serial Data-Word MSB Command Byte 0 RDAC EEMEM C3 C3 C2 C2 C1 C1 C0 C0 Data Byte 1 0 A3 0 A2 0 A1 0 A0 X D15 X D14 Data Byte 0 X D13 X D12 X D11 X D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 LSB D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Command instruction codes are defined in Table 7. Table 7.
PAGE 18
AD5231 Data Sheet ADVANCED CONTROL MODES makes the left-shift function as ideal a logarithmic adjustment as possible. Key programming features include: • Scratchpad programming to any desirable values • Nonvolatile memory storage of the scratchpad RDAC register value in the EEMEM register • Increment and decrement instructions for the RDAC wiper register The right-shift 4 and 5 instructions are ideal only if the LSB is 0 (ideal logarithmic = no error).
PAGE 19
Data Sheet AD5231 Using Additional Internal Nonvolatile EEMEM SWA A The AD5231 contains additional user EEMEM registers for storing any 16-bit data such as memory data for other components, look-up tables, or system identification information. Table 9 provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 28 bytes (14 addresses × 2 bytes each) of user EEMEM. SW(2N–1) Table 9.
PAGE 20
AD5231 Data Sheet The general transfer equation for this operation is 100 RWB RWB (D) = 75 1024 − D × R AB + RW 1024 (2) For example, the output resistance values in Table 12 are set for the RDAC latch codes with VDD = 5 V (applies to RAB = 10 kΩ digital potentiometers). 50 Table 12. RWA(D) at Selected Codes for RAB = 10 kΩ D (DEC) 1023 512 1 0 25 0 0 256 512 CODE (Decimal) 768 1023 02739-043 RWA (D), RWB (D); (% of Nominal RAB) RWA Figure 44. RWA(D) and RWB(D) vs.
PAGE 21
Data Sheet AD5231 PROGRAMMING EXAMPLES Table 17. Storing Additional User Data in EEMEM The following programming examples illustrate a typical sequence of events for various features of the AD5231. See Table 7 for the instructions and data-word format. The instruction numbers, addresses, and data appearing at SDI and SDO pins are in hexadecimal format. Table 13. Scratchpad Programming SDI 0xB00100 SDO 0xXXXXXX Action Writes data 0x100 into RDAC register, Wiper W moves to 1/4 full-scale position.
PAGE 22
AD5231 Data Sheet FLASH/EEMEM RELIABILITY The Flash/EE memory array on the AD5231 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events.
PAGE 23
Data Sheet AD5231 APPLICATIONS BIPOLAR OPERATION FROM DUAL SUPPLIES VDD U2 AD5231 A W B A B Vi U1 GND SCLK MOSI A W GND VSS D = MIDSCALE –2.5V HIGH VOLTAGE OPERATION The digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across Terminals A–B, Terminals W–A, or Terminals W–B does not exceed |5 V|.
PAGE 24
AD5231 Data Sheet PROGRAMMABLE CURRENT SOURCE +5V U1 W +5V A A2 R VIN VOUT +5V +2.5VREF TRIM GND –5V –2.5VREF VIN 3 V+ AD8552 V– SLEEP VOUT GND A1 –5V –2.048V TO VL V+ RS 102Ω OP1177 U2 V– –5V VL RL 100Ω IL Figure 52. Programmable Current Source 5V AD5231 U1 3 VIN V OUT A W REF191 is a unique low supply, headroom precision reference that can deliver the 20 mA needed at 2.048 V.
PAGE 25
Data Sheet AD5231 RESISTANCE SCALING For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution. If the resistors are matched, the load current is (R2A + R2B ) × VW (8) R2 15kΩ A1 A2 W1 B1 C1 +15V 10pF – +15V A + AD5231 B W –2.5V V+ OP2177 – V– In voltage diver mode, by paralleling a discrete resistor as shown in Figure 55, a proportionately lower voltage appears at Terminals A–B.
PAGE 26
AD5231 Data Sheet RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external load dominates the ac characteristics of the RDACs. The −3 dB bandwidth of the AD5231BRU10 (10 kΩ resistor) measures 370 kHz at half scale when configured as a potentiometer divider. Figure 15 provides the large signal BODE plot characteristics. A parasitic simulation mode is shown in Figure 57. RDAC 10kΩ B CA 50pF CB 50pF CW 50pF W .PARAM D = 1024, RDAC = 10E3 * .
PAGE 27
Data Sheet AD5231 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 58.
PAGE 28
AD5231 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2001–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02739-0-3/13(D) Rev.