Datasheet

AD5228
Rev. A | Page 14 of 20
LAYOUT AND POWER SUPPLY BIASING
POWER-UP AND POWER-DOWN SEQUENCES
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 39 illustrates the basic supply bypassing configu-
ration for the AD5228.
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (Figure 39), it is
important to power on V
DD
before applying any voltage to
Terminals A, B, and W. Otherwise, the diodes are forward-
biased such that V
DD
is powered on unintentionally and can
affect other parts of the circuit. Similarly, V
DD
should be
powered down last. The ideal power-on sequence is in the
following order: GND, V
DD
, and V
A/B/W
. The order of powering
V
A
, V
B
, and V
W
is not important as long as they are powered on
after V
DD
. The states of the
PU
and
PD
pins can be logic high or
floating, but they should not be logic low during power-on.
04422-0-041
V
DD
V
DD
+
GND
AD5228
C2
10μF
C1
0.1μF
Figure 40. Power Supply Bypassing