Datasheet

AD5227
Rev. B | Page 4 of 16
Parameter Symbol Conditions Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts
6, 10
)
Clock Frequency f
CLK
50 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 10 ns
CS to CLK Setup Time
t
CSS
10 ns
CS
Rise to CLK Hold Time
t
CSH
10 ns
U/D
to Clock Fall Setup Time
t
UDS
10 ns
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
NL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= V.
10
All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
V
DD
= 5 V.
INTERFACE TIMING DIAGRAMS
04419-0-004
CS = LOW
U/D = HIGH
CLK
R
WB
Figure 2. Increment R
WB
04419-0-005
CS = LOW
U/D = 0
CLK
R
WB
Figure 3. Decrement R
WB
04419-0-006
1
0
1
0
1
0
CS
CLK
U/D
R
WB
t
S
t
UDS
t
CL
t
CH
t
CSS
t
CSH
Figure 4. Detailed Timing Diagram (Only R
WB
Decrement Shown)