Datasheet

–2–
REV.
AD5220–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
= NC, R
AB
= 10 kΩ –1 ±0.4 +1 LSB
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
= NC, R
AB
= 10 kΩ –1 ±0.5 +1 LSB
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance ∆RT
A
= +25°C –30 +30 %
Resistance Temperature Coefficient ∆R
AB
/∆TV
AB
= V
DD
, Wiper = No Connect 800 ppm/°C
Wiper Resistance R
W
I
W
= V
DD
/R, V
DD
= +3 V or +5 V 40 100 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution N 7 Bits
Integral Nonlinearity
3
INL R
AB
= 10 kΩ –1 ±0.5 +1 LSB
R
AB
= 50 kΩ, 100 kΩ –0.5 ±0.2 +0.5 LSB
Differential Nonlinearity Error
3
DNL R
AB
= 10 kΩ –1 ±0.4 +1 LSB
R
AB
= 50 kΩ, 100 kΩ –0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient ∆V
W
/∆T Code = 40
H
20 ppm/°C
Full-Scale Error V
WFSE
Code = 7F
H
–2 –0.5 0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.5 +1 LSB
RESISTOR TERMINALS
Voltage Range
4
V
A,
V
B,
V
W
0V
DD
V
Capacitance
5
A, B C
A,
C
B
f = 1 MHz, Measured to GND, Code = 40
H
10 pF
Capacitance
5
WC
W
f = 1 MHz, Measured to GND, Code = 40
H
48 pF
Common-Mode Leakage I
CM
V
A
= V
B
= V
W
7.5 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
V
DD
= +5 V/+3 V 2.4/2.1 V
Input Logic Low V
IL
V
DD
= +5 V/+3 V 0.8/0.6 V
Input Current I
IL
V
IN
= 0 V or +5 V ±1 µA
Input Capacitance
5
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
2.7 5.5 V
Supply Current I
DD
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V 15 40 µA
Power Dissipation
6
P
DISS
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V 75 200 µW
Power Supply Sensitivity PSS 0.004 0.015 %/%
DYNAMIC CHARACTERISTICS
5, 7, 8
Bandwidth –3 dB BW_10K R
AB
= 10 kΩ, Code = 40
H
650 kHz
BW_50K R
AB
= 50 kΩ, Code = 40
H
142 kHz
BW_100K R
AB
= 100 kΩ, Code = 40
H
69 kHz
Total Harmonic Distortion THD
W
V
A
=1 V rms + 2.5 V dc, V
B
= 2.5 V dc, f = 1 kHz 0.002 %
V
W
Settling Time t
S
V
A
= V
DD
, V
B
= 0 V, 50% of Final Value,
10K/50K/100K 0.6/3/6 µs
Resistor Noise Voltage e
NWB
R
WB
= 5 kΩ, f = 1 kHz 14 nV/√Hz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 9
Input Clock Pulsewidth t
CH
, t
CL
Clock Level High or Low 25 ns
CS to CLK Setup Time t
CSS
20 ns
CS Rise to Clock Hold Time t
CSH
20 ns
U/D to Clock Fall Setup Time t
UDS
10 ns
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
DD
= +5 V.
9
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V.
Specifications subject to change without notice.
(V
DD
= +3 V ⴞ 10% or +5 V ⴞ 10%, V
A
= +V
DD
, V
B
= 0 V, –40ⴗC < T
A
< +85ⴗC unless
otherwise noted)
A