Datasheet

AD5204/AD5206
Rev. C | Page 5 of 20
TIMING DIAGRAMS
06884-003
SDI
CLK
V
OUT
CS
1
0
1
0
1
0
V
DD
0V
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC LATCH LOAD
Figure 3. Timing Diagram
SDI
(DATA IN)
SDO
(DATA OUT)
1
0
1
0
1
0
1
0
V
DD
0V
CLK
CS
V
OUT
Ax OR Dx Ax OR Dx
Ax OR Dx Ax OR Dx
t
CSS
t
DH
t
PD_MAX
t
CSH0
±1 LSB ERROR BAND
±1 LSB
t
CSH1
t
CH
t
CSW
t
S
t
CL
t
DS
t
CS1
06884-004
Figure 4. Detailed Timing Diagram
±1 LSB
±1 LSB ERROR BAND
1
0
V
DD
0V
V
OUT
t
RS
t
S
PR
0
6884-005
Figure 5. AD5204 Preset Timing Diagram