Datasheet

AD5204/AD5206
Rev. C | Page 16 of 20
TEST CIRCUITS
340kΩ
V
SS
LOGIC
06884-050
Figure 25. ESD Protection of Digital Pins
A, B, W
06884-051
V
SS
Figure 26. ESD Protection of Resistor Terminals
V+
DUT
V
MS
A
B
W
V+ = V
DD
1LSB = V+/256
06884-036
Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
DUT
V
MS
A
B
W
NO CONNECT
I
W
06884-037
Figure 28. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V+
A
B
W
DUT
I
MS
V
MS
I
W
= 1V/R
NOMINAL
I
W
V
W
V+ V
DD
R
W
=
WHERE V
W1
= V
MS
WHEN I
W
= 0
AND V
W2
= V
MS
WHEN I
W
= 1/R
V
W2
– [V
W1
+ I
W
(R
AW
II R
BW
)]
0
6884-052
Figure 29. Wiper Resistance Test Circuit
V+
A
B
W
~
V
A
V
MS
V
DD
V+ = V
DD
± 10%
PSRR (dB) = 20 log
∆V
MS
∆V
DD
PSS (%/%) =
∆V
MS
%
∆V
DD
%
( )
0
6884-039
Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A
V
IN
OFFSET BIAS
OP279
5V
V
OUT
DUT
W
OFFSET
GND
B
0
6884-040
Figure 31. Inverting Programmable Gain Test Circuit
A
V
IN
OFFSET BIAS
OP279
5
V
V
OUT
DUT
W
OFFSET
GND
B
06884-041
Figure 32. Noninverting Programmable Gain Test Circuit
B
A
V
IN
2.5V
+15V
V
OUT
DUT
W
–15V
O
FFSET
GND
OP42
0
6884-042
Figure 33. Gain vs. Frequency Test Circuit
DUT
I
SW
B
W
V
SS
TO V
DD
R
SW
=
0.1
V
I
SW
CODE = 0x00
0.1V
+
–
06884-043
Figure 34. Incremental On-Resistance Test Circuit