Datasheet

–4–
AD5200/AD5201–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth t
CH
, t
CL
Clock Level High or Low 20 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CS Setup Time t
CSS
15 ns
CS High Pulsewidth t
CSW
40 ns
CLK Fall to CS Fall Hold Time t
CSH0
0ns
CLK Fall to CS Rise Hold Time t
CSH1
0ns
CS Rise to Clock Rise Setup t
CS1
10 ns
NOTES
1
Typicals represent average readings at 25°C and V
DD
= 5 V, V
SS
= 0 V.
2
Guaranteed by design and not subject to production test.
3
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using V
LOGIC
= 5 V.
Specifications subject to change without notice.
(V
DD
= 5 V  10%, or 3 V  10%, V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V, –40C < T
A
< +85C
unless otherwise noted.)
D7 D6 D5 D4 D3 D2 D1 D0
0
1
SDI
0
1
CLK
0
1
VOUT
0
1
CS
DAC REGISTER LOAD
Figure 1a. AD5200 Timing Diagram
0
1
SDI D5D4D3D2D1D0
0
1
CLK
0
1
CS
DAC REGISTER LOAD
0
1
VOUT
Figure 1b. AD5201 Timing Diagram
Dx Dx
0
1
0
1
0
1
0
V
DD
SDI
(DATA IN)
CLK
CS
VOUT
t
CH
t
DS
t
DH
t
CS1
t
CSW
t
S
t
CL
t
CSH0
t
CSS
1LSB
t
CSH1
Figure 1c. Detail Timing Diagram