Datasheet

AD5175
Rev. A | Page 5 of 20
Limit at T
MIN
, T
MAX
Parameter Conditions
1
Min Max Unit Description
t
RDAC_R-PERF
2 µs RDAC register write command execute time (R-Perf mode)
t
RDAC_NORMAL
600 ns RDAC register write command execute time (normal mode)
t
MEMORY_READ
6 µs Memory readback execute time
t
MEMORY_PROGRAM
350 ms Memory program time
t
RESET
600 µs Reset 50-TP restore time
t
POWER-UP
6
2 ms Power-on 50-TP restore time
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4
Refer to t
RDAC_R-PERF
and t
RDAC_NORMAL
for RDAC register write operations.
5
Refer to t
MEMORY_READ
and
t
MEMORY_PROGRAM
for memory commands operations.
6
Maximum time after V
DD
− V
SS
is equal to 2.5 V.
Shift Register and Timing Diagrams
DATA BITS
DB9 (MSB) DB0 (LSB)
D7
D6 D5
D4
D3
D2 D1
D0
CONTROL BITS
C0 C1
C2
D9
D8
C3
0 0
0
8719-003
Figure 2. Shift Register Content
RESET
t
7
t
6
t
2
t
4
t
11
t
12
t
6
t
5
t
10
t
1
SCL
SDA
PS S P
t
3
t
8
t
9
t
1
3
0
8719-002
Figure 3. 2-Wire I
2
C Timing Diagram