Datasheet

AD5175
Rev. A | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
4, 10
Bandwidth −3 dB, R
AW
= 5 kΩ, Terminal W, see Figure 23 700 kHz
Total Harmonic Distortion V
A
= 1 V rms, f = 1 kHz, R
AW
= 5 kΩ −90 dB
Resistor Noise Density R
WB
= 5 kΩ, T
A
= 25°C, f = 10 kHz 13 nV/√Hz
1
Typical specifications represent average readings at 25°C, V
DD
= 5 V, and V
SS
= 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3
The maximum current in each code is defined by I
AW
= (V
DD
− 1)/R
AW
.
4
Guaranteed by design and not subject to production test.
5
See Figure 8 for more details.
6
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
7
Different from operating current; the supply current for the fuse program lasts approximately 55 ms.
8
Different from operating current; the supply current for the fuse read lasts approximately 500 ns.
9
P
DISS
is calculated from (I
DD
× V
DD
) + (I
SS
× V
SS
).
10
All dynamic characteristics use V
DD
= +2.5 V, V
SS
= −2.5 V.
INTERFACE TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Limit at T
MIN
, T
MAX
Parameter Conditions
1
Min Max Unit Description
f
SCL
2
Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz Serial clock frequency
t
1
Standard mode 4 µs t
HIGH
, SCL high time
Fast mode 0.6 µs t
HIGH
, SCL high time
t
2
Standard mode 4.7 µs t
LOW
, SCL low time
Fast mode 1.3 µs t
LOW
, SCL low time
t
3
Standard mode 250 ns t
SU;DAT
, data setup time
Fast mode 100 ns t
SU;DAT
, data setup time
t
4
Standard mode 0 3.45 µs t
HD;DAT
, data hold time
Fast mode 0 0.9 µs t
HD;DAT
, data hold time
t
5
Standard mode 4.7 µs t
SU;STA
, set-up time for a repeated start condition
Fast mode 0.6 µs t
SU;STA,
set-up time for a repeated start condition
t
6
Standard mode 4 µs t
HD;STA
, hold time (repeated) start condition
Fast mode 0.6 µs t
HD;STA
, hold time (repeated) start condition
High speed mode 160 ns t
HD;STA
, hold time (repeated) start condition
t
7
Standard mode 4.7 µs t
BUF
, bus free time between a stop and a start condition
Fast mode 1.3 µs t
BUF
, bus free time between a stop and a start condition
t
8
Standard mode 4 µs t
SU;STO
, setup time for a stop condition
Fast mode 0.6 µs t
SU;STO
, setup time for a stop condition
t
9
Standard mode 1000 ns t
RDA
, rise time of the SDA signal
Fast mode 300 ns t
RDA
, rise time of the SDA signal
t
10
Standard mode 300 ns t
FDA
, fall time of the SDA signal
Fast mode 300 ns t
FDA
, fall time of the SDA signal
t
11
Standard mode 1000 ns t
RCL
, rise time of the SCL signal
Fast mode 300 ns t
RCL
, rise time of the SCL signal
t
11A
Standard mode 1000 ns
t
RCL1
, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
Fast mode 300 ns
t
RCL1
, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
t
12
Standard mode 300 ns t
FCL
, fall time of the SCL signal
Fast mode 300 ns t
FCL
, fall time of the SCL signal
t
13
RESET
pulse time
20 ns
Minimum RESET low time
t
SP
3
Fast mode 0 50 ns Pulse width of the spike is suppressed
t
EXEC
4, 5
500 ns Command execute time