Datasheet

AD5175
Rev. A | Page 19 of 20
Calculate the Actual End-to-End Resistance
TERMINAL VOLTAGE OPERATING RANGE
The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance
can, therefore, be calculated (which is valuable for calibration,
tolerance matching, and precision applications).
The positive V
DD
and negative V
SS
power supplies of the AD5175
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed V
DD
or V
SS
are clamped by the internal
forward-biased diodes (see Figure 30).
The resistance tolerance in percentage is stored in fixed-point
format, using a 16-bit sign magnitude binary. The sign bit(0 =
negative and 1 = positive) and the integer part is located in
Address 0x39, as shown in Table 11. Address 0x3A contains
the fractional part, as shown in Table 12.
V
SS
V
DD
A
W
0
8719-109
That is, if the data readback from Address 0x39 is 0000001010
and data from Address 0x3A is 0010110000, then the end-to-end
resistance can be calculated as follows.
For Memory Location 0x39,
DB[9:8]: XX = don’t care

DB[7]: 0 = negative
Figure 30. Maximum Terminal Voltages Set by V
DD
and V
SS
DB[6:0]: 0001010 = 10
The ground pin of the AD5175 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join
the AD5175 ground terminal remotely to the common ground.
The digital input control signals to the AD5175 must be refe-
renced to the device ground pin (GND) and satisfy the logic
level defined in the Specifications section. An internal level
shift circuit ensures that the common-mode voltage range of
the three terminals extends from V
SS
to V
DD
, regardless of the
digital input level.
For Memory Location 0x3A,
DB[9:8]: XX = don’t care
DB[7:0]: 10110000 = 176 × 2
−8
= 0.6875
Therefore, tolerance = −10.6875% and R
WA
(1023)= 8.931 kΩ.
EXT_CAP CAPACITOR
A 1 μF capacitor to V
SS
must be connected to the EXT_CAP pin
(see Figure 29) on power-up and throughout the operation of
the AD5175.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Termi nal A a nd Ter m inal W ( s e e Figure 30), it is important to
power V
DD
/V
SS
first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that V
DD
/V
SS
are powered unintentionally. The ideal power-up
sequence is V
SS
, GND, V
DD
, digital inputs, V
A
, and V
W
. The
order of powering V
A
, V
W
, and digital inputs is not important
as long as they are powered after V
DD
/V
SS
.
AD5175
50-TP
MEMORY
BLOCK
EXT_CAP
C1
1µF
V
SS
V
SS
0
8719-009
As soon as V
DD
is powered, the power-on preset activates,
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.
Figure 29. EXT_CAP Hardware Setup
Table 12. End-to-End Resistance Tolerance Bytes
Data Byte
1
Memory Map Address DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0x39 X X Sign 2
6
2
5
2
4
2
3
2
2
2
1
2
0
0x3A X X 2
−1
2
−2
2
−3
2
−4
2
−5
2
−6
2
−7
2
−8
1
X is don’t care.