Datasheet

AD5174
Rev. B | Page 5 of 20
Shift Register and Timing Diagrams
DATA BITS
DB9 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
CONTROL BITS
C0C1
C2
D9
D8
C3
00
08718-002
Figure 2. Shift Register Content
0 0 C3 C2 D7 D6 D5 D2 D1 D0
SCLK
SDO
DIN
SYNC
t
7
t
9
t
1
t
2
t
4
t
3
t
8
t
5
t
6
08718-003
Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1
t
10
t
9
00 00C3 C3
X X C3 D1 D0
D1 D0D0 D0
SCLK
SDO
DIN
SYNC
08718-004
Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1