Datasheet

AD5174
Rev. B | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
4, 10
Bandwidth −3 dB, R
AW
= 5 kΩ, Terminal W, see Figure 24 700 kHz
Total Harmonic Distortion V
A
= 1 V rms, f = 1 kHz, R
AW
= 5 kΩ −90 dB
Resistor Noise Density R
WB
= 5 kΩ, T
A
= 25°C, f = 10 kHz 13 nV/√Hz
1
Typical specifications represent average readings at 25°C, V
DD
= 5 V, and V
SS
= 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions.
3
The maximum current in each code is defined by I
AW
= (V
DD
− 1)/R
AW
.
4
Guaranteed by design and not subject to production test.
5
See Figure 9 for more details.
6
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
7
Different from operating current; the supply current for the fuse program lasts approximately 55 ms.
8
Different from operating current; the supply current for the fuse read lasts approximately 500 ns.
9
P
DISS
is calculated from (I
DD
× V
DD
) + (I
SS
× V
SS
).
10
All dynamic characteristics use V
DD
= +2.5 V, V
SS
= −2.5 V.
INTERFACE TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, V
SS
= 0 V; V
DD
= 2.5 V, V
SS
= −2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
10 ns min SCLK high time
t
3
10 ns min SCLK low time
t
4
15 ns min
SYNC
to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
1 ns min
SCLK falling edge to SYNC
rising edge
t
8
3
400 ns min
Minimum SYNC
high time
t
9
15 ns min
SYNC
rising edge to next SCLK fall ignored
t
10
4
450 ns max SCLK rising edge to SDO valid
t
MEMORY_READ
6 μs max Memory readback execute time
t
MEMORY_PROGRAM
350 ms max Memory program time
t
RESET
600 μs max Reset OTP restore time
t
POWER-UP
5
2 ms max Power-on 50-TP restore time
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 50 MHz.
3
Refer to t
MEMORY_READ
and
t
MEMORY_PROGRAM
for memory commands operations.
4
R
PULL_UP
= 2.2 kΩ to V
DD
with a capacitance load of 168 pF.
5
Maximum time after V
DD
− V
SS
is equal to 2.5 V.