Datasheet

AD5174
Rev. B | Page 17 of 20
EXT_CAP CAPACITOR
A 1 μF capacitor to V
SS
must be connected to the EXT_CAP
pin, as shown in Figure 28, on power-up and throughout the
operation of the AD5174.
AD5174
50-TP
MEMORY
BLOCK
EXT_CAP
C1
1µF
V
SS
V
SS
08718-008
Figure 28. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive V
DD
and negative V
SS
power supplies of the AD5174
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed V
DD
or V
SS
are clamped by the internal
forward-biased diodes (see Figure 29).
V
SS
V
DD
A
W
08718-009
Figure 29. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pin of the AD5174 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join the
AD5174 ground terminal remotely to the common ground. The
digital input control signals to the AD5174 must be referenced
to the device ground pin (GND) and must satisfy the logic level
defined in the Specifications section. An internal level shift
circuit ensures that the common-mode voltage range of the
three terminals extends from V
SS
to V
DD
, regardless of the
digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Ter minal W (see Figure 29), it is important to
power V
DD
/V
SS
first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that V
DD
/V
SS
are powered unintentionally. The ideal power-
up sequence is V
SS
, GND, V
DD
, digital inputs, V
A
, and V
W
.
The order of powering V
A
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/V
SS
.
As soon as V
DD
is powered, the power-on preset activates,
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.