Datasheet

AD5172/AD5173 Data Sheet
Rev. I | Page 6 of 28
Parameter Symbol Conditions Min Typ
1
Max Unit
POWER SUPPLIES
Power Supply Range V
DD_RANGE
2.7 5.5 V
OTP Supply Voltage
9, 10
V
DD_OTP
T
A
= 25°C 5.6 5.7 5.8 V
Supply Current I
DD
V
IH
= 5 V or V
IL
= 0 V 3.5 6 µA
OTP Supply Current
9, 11, 12
I
DD_OTP
V
DD_OTP
= 5.0 V, T
A
= 25°C
100
mA
Power Dissipation
13
P
DISS
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
33 µW
Power Supply Sensitivity PSS V
DD
= 5 V ± 10%,
code = midscale
±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS
14
Bandwidth, −3 dB BW R
AB
= 10 kΩ, code = 0x80 600 kHz
R
AB
= 50 kΩ, code = 0x80 100 kHz
R
AB
= 100 kΩ, code = 0x80 40 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 kΩ
0.1 %
V
W
Settling Time t
S
V
A
= 5 V, V
B
= 0 V, ±1 LSB
error band
2 µs
Resistor Noise Voltage Density e
N_WB
R
WB
= 5 kΩ, R
S
= 0 Ω 9 nV/√Hz
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, V
B
= 0 V, wiper (V
W
) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the V
IH
is 0.7 V × V
DD
. For example, V
IH
minimum = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V
DD
.
However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use V
DD
= 5 V.