Datasheet

Data Sheet AD5172/AD5173
Rev. I | Page 17 of 28
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
0
4103-028
Figure 41. AD5172/AD5173 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between W and B is
W
AB
WB
RR
D
DR  2
128
)(
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if R
AB
is 10 kΩ and the A terminal is open circuited,
the output resistance, R
WB
, is set according to the RDAC latch
codes, as listed in Table 8.
Table 8. Codes and Corresponding R
WB
Resistance
D (Dec) R
WB
(Ω) Output State
255 9961 Full scale (R
AB
– 1 LSB + R
W
)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible destruc-
tion of the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digi-
tally controlled complementary resistance, R
WA
. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA
RR
D
DR  2
128
–256
)(
(2)
When R
AB
is 10 kΩ and the B terminal is open circuited, the
output resistance, R
WA
, is set according to the RDAC latch
codes, as listed in Table 9.
Table 9. Codes and Corresponding R
WA
Resistance
D (Dec) R
WA
(Ω) Output State
255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale
Typical device-to-device matching is process-lot dependent
and can vary up to ±30%. Because the resistance element is
processed using thin-film technology, the change in R
AB
with
temperature has a very low temperature coefficient of 35 ppm/°C.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and at wiper to A, proportional to the input voltage
at A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04103-029
Figure 42. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the vol-
tage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at V
W
with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
DV
256
256
256
)(


(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
B
AB
WA
A
AB
WB
W
V
R
DR
V
R
DR
DV
)(
)(
)(  (4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
WA
and R
WB
, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.