Datasheet

AD5171
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
V
DD
= 3 V to 5 V ± 10%, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS
2, 3
)
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time Between Start and Stop t
1
1.3 μs
t
HD;STA
Hold Time (Repeated Start) t
2
After this period, the
first clock pulse is generated
0.6 μs
t
LOW
Low Period of SCL Clock t
3
1.3 μs
t
HIGH
High Period of SCL Clock t
4
0.6 50 μs
t
SU;STA
Setup Time for Start Condition t
5
0.6 μs
t
HD;DAT
Data Hold Time t
6
0.9 μs
t
SU;DAT
Data Setup Time t
7
0.1 μs
t
F
Fall Time of Both SDA and SCL Signals t
8
0.3 μs
t
R
Rise Time of Both SDA and SCL Signals t
9
0.3 μs
t
SU;STO
Setup Time for Stop Condition t
10
0.6 μs
OTP Program Time t
11
400 ms
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design; not subject to production test.
3
All dynamic characteristics use V
DD
= 5 V.
SCL
S
DA
t
1
t
2
t
3
t
8
t
8
t
9
t
4
t
5
t
9
t
7
t
6
t
10
PPS
03437-024
Figure 3. Interface Timing Diagram