Datasheet

AD5170
Rev. G | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
B
1
A
2
AD0
3
G
ND 4
V
DD
5
W
10
NC
9
AD1
8
SDA 7
SCL 6
AD5170
TOP VIEW
(Not to Scale)
04104-048
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 B B Terminal. GND ≤ V
B
≤ V
DD
.
2 A A Terminal. GND ≤ V
A
≤ V
DD
.
3 AD0 Programmable Address Bit 0 for Multiple Package Decoding.
4 GND Digital Ground.
5 V
DD
Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, the V
DD
supply must be
within the 5.6 V to 5.8 V range and capable of driving 100 mA.
6 SCL
Serial Clock Input. Positive edge triggered. Requires a pull-up resistor. If it is driven directly from a logic controller
without the pull-up resistor, ensure that V
IH
minimum is 0.7 V × V
DD
.
7 SDA
Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that V
IH
minimum is 0.7 V × V
DD
.
8 AD1 Programmable Address Bit 1 for Multiple Package Decoding.
9 NC No Connect.
10 W W Terminal. GND ≤ V
W
≤ V
DD
.