Datasheet

AD5170
Rev. G | Page 7 of 24
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
; V
B
= 0 V, −40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
1
(SPECIFICATIONS
APPLY TO ALL PARTS)
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time Between Stop and Start t
1
1.3 μs
t
HD;STA
Hold Time (Repeated Start) t
2
After this period, the first clock
pulse is generated
0.6 μs
t
LOW
Low Period of SCL Clock t
3
1.3 μs
t
HIGH
High Period of SCL Clock t
4
0.6 μs
t
SU;STA
Setup Time for Repeated Start Condition t
5
0.6 μs
t
HD;DAT
Data Hold Time
2
t
6
0.9 μs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for Stop Condition t
10
0.6 μs
OTP Program Time t
11
400 ms
1
See Figure 2 for locations of measured values.
2
The maximum t
HD;DAT
must be met only if the device does not stretch the low period (t
LOW
) of the SCL signal.
Timing Diagram
04104-044
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 2. I
2
C Interface Detailed Timing Diagram