Datasheet

AD5170
Rev. G | Page 6 of 24
Parameter Symbol Conditions Min Typ
1
Max Unit
POWER SUPPLIES
Power Supply Range V
DD RANGE
2.7 5.5 V
OTP Supply Voltage
8, 9
V
DD_OTP
5.6 5.7 5.8 V
Supply Current I
DD
V
IH
= 5 V or V
IL
= 0 V 3.5 6 μA
OTP Supply Current
8, 10, 11
I
DD_OTP
V
DD_OTP
= 5 V, T
A
= 25°C 100 mA
Power Dissipation
12
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V 33 μW
Power Supply Sensitivity PSS
V
DD
= 5 V ± 10%, code =
midscale
±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS
13
–3 dB Bandwidth BW R
AB
= 10 kΩ, code = 0x80 600 kHz
R
AB
= 50 kΩ, code = 0x80 100 kHz
R
AB
= 100 kΩ, code = 0x80 40 kHz
Total Harmonic Distortion THD
W
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 10 kΩ
0.1 %
V
W
Settling Time (10 kΩ/50 kΩ/100 kΩ) t
S
V
A
= 5 V, V
B
= 0 V, ±1 LSB error
band
2 μs
Resistor Noise Voltage Density e
N_WB
R
WB
= 5 kΩ, f = 1 kHz 9 nV/√Hz
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
The minimum voltage requirement on the V
IH
is 0.7 V × V
DD
. For example, V
IH
minimum = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up
to V
DD
. However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
9
Different from operating power supply, power supply OTP is used one time only.
10
Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11
See Figure 26 for the energy plot during OTP program.
12
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
13
All dynamic characteristics use V
DD
= 5 V.