Datasheet

AD5170
Rev. G | Page 16 of 24
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
SD BIT
04104-034
Figure 35. Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
W
AB
WB
RR
D
(D)R ×+×= 2
256
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if R
AB
= 10 kΩ and Terminal A is open-circuited,
the output resistance, R
WB
, is set for the RDAC latch codes, as
shown in Table 7.
Table 7. Codes and Corresponding R
WB
Resistance
D (Dec) R
WB
(Ω) Output State
255 9961 Full scale (R
AB
− 1 LSB + R
W
)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
betwe en Termina l W and Ter minal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper (Terminal W) and Terminal A also
produces a digitally controlled, complementary resistance, R
WA
.
When these terminals are used, Terminal B can be opened.
Setting the resistance value for R
WA
starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
W
ABWA
RR
D
(D)R ×+×= 2
256
–256
(2)
For R
AB
= 10 kΩ and Terminal B open circuited, Table 8 shows
some examples of the output resistance (R
WA
) vs. the RDAC
latch codes.
Table 8. Codes and Corresponding R
WA
Resistance
D (Dec) R
WA
(Ω) Output State
255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale
Typical device-to-device matching is process-lot dependent
and can vary by up to ±30%. Because the resistance element is
processed using thin film technology, the change in R
AB
with
temperature has a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER—
VOLTAGE OUTPUT OPERATION
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
W
B
V
I
V
O
0
4104-035
Figure 36. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground pro-
duces an output voltage at the wiper to B starting at 0 V up to
1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V
W
with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
DV
256
256
256
)(
−
+=
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, V
W
, the following equation can be used:
B
AB
WA
A
AB
WB
W
V
R
DR
V
R
DR
DV
)(
)(
)( += (4)
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors, R
WA
and R
WB
, and not the absolute values.
Therefore, the temperature drift reduces to 15 ppm/°C.