Datasheet

AD5160
Rev. B | Page 5 of 16
TIMING CHARACTERISTICS—ALL VERSIONS
V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
1, 2
Specifications apply to all parts
Clock Frequency f
CLK
25 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CS Setup Time
t
CSS
15 ns
CS High Pulse Width
t
CSW
40 ns
CLK Fall to CS Fall Hold Time
t
CSH0
0 ns
CLK Fall to CS Rise Hold Time
t
CSH1
0 ns
1
See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a
voltage level of 1.5 V.
2
Guaranteed by design and not subject to production test.