Datasheet

AD5122/AD5142 Data Sheet
Rev. 0 | Page 8 of 32
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
9
Bandwidth BW −3 dB
R
AB
= 10 kΩ 3 MHz
R
AB
= 100 kΩ 0.43 MHz
Total Harmonic Distortion
THD
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
V
B
= 0 V, f = 1 kHz
R
AB
= 10 kΩ −80 dB
R
AB
= 100 kΩ −90 dB
Resistor Noise Density e
N_WB
Code = half scale, T
A
= 25°C,
f = 10 kHz
R
AB
= 10 kΩ 7 nV/√Hz
R
AB
= 100 kΩ 20 nV/√Hz
V
W
Settling Time t
S
V
A
= 5 V, V
B
= 0 V, from
zero scale to full scale,
±0.5 LSB error band
R
AB
= 10 kΩ
2
µs
R
AB
= 100 kΩ 12 µs
Crosstalk (C
W1
/C
W2
) C
T
R
AB
= 10 kΩ 10 nV-sec
R
AB
= 100 kΩ 25 nV-sec
Analog Crosstalk C
TA
−90 dB
Endurance
10
T
A
= 25°C 1 Mcycles
100 kcycles
Data Retention
11
50 Years
1
Typical values represent average readings at 25°C, V
DD
= 5 V, V
SS
= 0 V, and V
LOGIC
= 5 V.
2
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × V
DD
)/R
AB
.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at V
WB
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
P
DISS
is calculated from (I
DD
× V
DD
) + (I
LOGIC
× V
LOGIC
).
9
All dynamic characteristics use V
DD
/V
SS
= ±2.5 V, and V
LOGIC
= 2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.