Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- Theory of Operation
- RDAC Register and EEPROM
- Input Shift Register
- SPI Serial Data Interface
- Advanced Control Modes
- EEPROM or RDAC Register Protection
- INDEP Pin
- RDAC Architecture
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- Terminal Voltage Operating Range
- Power-Up Sequence
- Layout and Power Supply Biasing
- Outline Dimensions
AD5122/AD5142 Data Sheet
Rev. 0 | Page 26 of 32
Table 17. Address Bits
A3 A2 A1 A0
Potentiometer Mode Linear Gain Setting Mode
Stored Channel
Memory Input Register RDAC Register Input Register RDAC Register
1 X
1
X
1
X
1
All channels All channels All channels All channels Not applicable
0 0 0 0 RDAC1 RDAC1 R
WB1
R
WB1
RDAC1/R
WB1
0 1 0 0 Not applicable Not applicable R
AW1
R
AW1
Not applicable
0 0 0 1 RDAC2 RDAC2 R
WB2
R
WB2
R
AW1
0 1 0 1 Not applicable Not applicable R
AW2
R
AW2
Not applicable
0 0 1 0 Not applicable Not applicable Not applicable Not applicable RDAC2/R
WB2
0 0 1 1 Not applicable Not applicable Not applicable Not applicable R
AW2
1
X = don’t care.
Table 18. Control Register Bit Descriptions
Bit Name Description
D0 RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
D1 EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
D2 Lineal setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode