Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- Theory of Operation
- RDAC Register and EEPROM
- Input Shift Register
- SPI Serial Data Interface
- Advanced Control Modes
- EEPROM or RDAC Register Protection
- INDEP Pin
- RDAC Architecture
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- Terminal Voltage Operating Range
- Power-Up Sequence
- Layout and Power Supply Biasing
- Outline Dimensions

Data Sheet AD5122/AD5142
Rev. 0 | Page 19 of 32
TEST CIRCUITS
Figure 34 to Figure 38 define the test conditions used in the Specifications section.
A
W
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
10880-034
Figure 34. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
A
W
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V+/2
N
10880-035
Figure 35. Potentiometer Divider Nonlinearity Error (INL, DNL)
A
W
NC
B
DUT
I
W
= V
DD
/R
NOMINAL
V
MS1
V
W
R
W
= V
MS1
/I
W
NC = NO CONNECT
10880-036
Figure 36. Wiper Resistance
A
W
B
V
MS
V+ = V
DD
±10%
PSRR (dB) = 20 LOG
V
MS
ΔV
DD
(
)
~
V
A
V
DD
Δ
V
MS
%
Δ
V
DD
%
PSS (%/%) =
V+
Δ
10880-037
Figure 37. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
+
–
DUT
CODE = 0x00
0.1V
V
SS
T
O V
DD
R
SW
=
0.1V
I
SW
I
SW
W
B
A
= NC
10880-038
Figure 38. Incremental On Resistance