Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- Theory of Operation
- RDAC Register and EEPROM
- Input Shift Register
- SPI Serial Data Interface
- Advanced Control Modes
- EEPROM or RDAC Register Protection
- INDEP Pin
- RDAC Architecture
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- Terminal Voltage Operating Range
- Power-Up Sequence
- Layout and Power Supply Biasing
- Outline Dimensions

Data Sheet AD5122/AD5142
Rev. 0 | Page 11 of 32
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 6.
Parameter Rating
V
DD
to GND −0.3 V to +7.0 V
V
SS
to GND +0.3 V to −7.0 V
V
DD
to V
SS
7 V
V
LOGIC
to GND −0.3 V to V
DD
+ 0.3 V or
+7.0 V (whichever is less)
V
A
, V
W
, V
B
to GND V
SS
− 0.3 V, V
DD
+ 0.3 V or
+7.0 V (whichever is less)
I
A
, I
W
, I
B
Pulsed
1
Frequency > 10 kHz
R
AW
= 10 kΩ ±6 mA/d
2
R
AW
= 100 kΩ ±1.5 mA/d
2
Frequency ≤ 10 kHz
R
AW
= 10 kΩ ±6 mA/√d
2
R
AW
= 100 kΩ ±1.5 mA/√d
2
Digital Inputs −0.3 V to V
LOGIC
+ 0.3 V or
+7 V (whichever is less)
Operating Temperature Range, T
A
3
−40°C to +125°C
Maximum Junction Temperature,
T
J
Maximum
150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (T
J
max − T
A
)/θ
JA
ESD
4
4 kV
FICDM 1.5 kV
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
d = pulse duty factor.
3
Includes programming of EEPROM memory.
4
Human body model (HBM) classification.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 7. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
16-Lead LFCSP 89.5
1
3 °C/W
16-Lead TSSOP 150.4
1
27.6 °C/W
1
JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION