Datasheet

AD5122/AD5142 Data Sheet
Rev. 0 | Page 10 of 32
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BITS
DB8DB15 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
ADDRESS BITS
A0A1
A2
C2 C1 C0 A3C3
CONTROL BITS
DB7
10880-002
Figure 2. Input Shift Register Contents
C3
t
4
t
2
t
3
t
5
t
6
C2 C1
C0 D7
D6
D5 D2
D1
D0SDI
*PREVIOUS COMMAND RECEIVED.
SCLK
SYNC
C3*
SDO C2*
C1* C0*
D7*
D6* D5* D2*
D1*
D0*
t
8
t
9
t
10
t
7
t
1
10880-003
Figure 3. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1
C3
t
4
t
2
t
3
t
5
t
6
C2 C1 C0 D7 D6 D5 D2 D1 D0
SDI
*PREVIOUS COMMAND RECEIVED.
SCLK
SYNC
C3*
SDO
C2* C1* C0* D7* D6* D5* D2* D1* D0*
t
8
t
9
t
10
t
7
t
1
10880-004
Figure 4. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0
SCLK
SYNC
RESET
t
1
10880-005
Figure 5. Control Pins Timing Diagram