Datasheet
Data Sheet AD5122A/AD5142A
Rev. A | Page 27 of 32
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
AD5122A:
W
ABAW
RR
D
DR
128
)(
From 0x00 to 0x7F (5)
AD5142A:
W
ABAW
RR
D
DR
256
)(
From 0x00 to 0xFF (6)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance.
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current or to the pulse current specified in Table 5. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 39.
W
A
B
V
A
V
OUT
V
B
10939-039
Figure 39. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at V
W
with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
AB
AW
A
AB
WB
W
V
R
DR
V
R
DR
DV
)(
)(
)(
(7)
where:
R
WB
(D) can be obtained from Equation 1 and Equation 2.
R
AW
(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
AW
and R
WB
, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The AD5122A/AD5142A are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed V
DD
are
clamped by the forward-biased diode. There is no polarity
constraint between V
A
, V
W
, and V
B
, but they cannot be higher
than V
DD
or lower than V
SS
.
V
DD
A
W
B
V
SS
10939-040
Figure 40. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power up V
DD
first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that V
DD
is powered unintentionally. The
ideal power-up sequence is V
SS
, V
DD
, V
LOGIC
, digital inputs, and
V
A
, V
B
, and V
W
. The order of powering V
A
, V
B
, V
W
, and digital
inputs is not important as long as they are powered after V
SS
,
V
DD
, and V
LOGIC
. Regardless of the power-up sequence and the
ramp rates of the power supplies, once V
DD
is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 41 illustrates the basic supply bypassing configuration
for the AD5122A/AD5142A.
V
DD
V
LOGIC
V
DD
+
V
SS
C1
0.1µF
C3
10µF
+
C2
0.1µF
C4
10µF
V
SS
V
LOGIC
+
C5
0.1µF
C6
10µF
AD5122A/
AD5142A
GND
10939-041
Figure 41. Power Supply Bypassing